This is many times more than the current huge chips
In just a few years, TSMC will be able to produce giant chips that will be more than twice as large as the current record holders.
The new version of CoWoS packaging technology will allow TSMC to produce chips with packages measuring 120 x 120 mm in two to three years!
The current CoWoS technology allows TSMC to create silicon inserts that are approximately 3.3 times the size of the photomask. Thus, the CPU or GPU itself, eight HBM3/HBM3E memory stacks, I/O chiplets and others can total up to 2831 mm2 with a maximum substrate size of 80 & times; 80 mm.
The next generation of CoWoS_L, due to be ready for production in 2026, will be capable of using interposers that are approximately 5.5 times the size of the mesh. That is, an area of 4719 mm will be available for a set of chips. Such SiPs will also require larger wafers, and judging by the TSMC slide, we are talking about 100x100mm.
Already in 2027, TSMC will be able to create chips with a 120×120 mm substrate and an available area of 6864 mm2. Considering how much modern chips with much smaller sizes consume, we can assume that such monsters will require several kilowatts of energy.
Of course, the size and consumption of Cerebras chips, which actually occupy the entire 300 mm silicon wafer after cutting it to a square shape, are far from the specified TSMC solutions, but Cerebras represents a unique specialized solution, and the new version of CoWoS will allow create monstrous chips for a variety of tasks.