256 RISC-V chips in one megacluster. An enthusiast has created an unusual solution based on CH32V003 controllers

by alex

A year ago he created a similar cluster based on 16 chips

The author of the bitluni channel created a 256-core cluster of chips based on the RISC-V architecture.  

Blogger Bitluni, known for his DIY devices, built his own megacluster (as he called it himself) RISC-V of 256 chips a year after he created a supercluster (also the author’s own name) of 16 such chips. < /p>

Each supercluster consisted of 16 CH32V003 RISC-V microcontrollers connected by an 8-bit bus. Each supercluster contains its own LED because the author originally wanted to be able to display a line of text on that cluster.  

Bitluni installed superclusters in pairs on eight “blade cluster” designs. The author used two additional CH32V203 microcontrollers on each blade, which served as a bridge between each supercluster and the main 8-bit bus of the megacluster. 

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During the development process, the author encountered a number of problems that had to be solved one way or another. The megacluster ultimately consists of 256 48 MHz RISC-V microcontrollers and 17 144 MHz RISC-V chips. It includes 640 GPIO pins and 256 ADC circuits. In single processor mode, this megacluster can operate at a frequency of 14.7 GHz, although this figure in this case is not identical to what it would be if a single chip physically operated at such a colossal frequency.  

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